An MOS (metal-oxide-semiconductor) structure in semiconductor processing is created by superimposing several layers of conducting, insulating and transistor-forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers.
CMOS is so-named because it uses two types of transistors, namely an n-type transistor (NMOS) and a p-type transistor (PMOS). These are fabricated in a semiconductor substrate, typically silicon, by using either negatively doped silicon that is rich in electrons or positively doped silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions with the desired concentration of produced holes or electrons.
NMOS remained the dominant MOS technology as long as the integration level devices on a chip was sufficiently low. It is comparatively inexpensive to fabricate, very functional dense, and faster than PMOS. With the dawning of large scale integration, however, power consumption in NMOS circuits began to exceed tolerable limits. CMOS represented a lower-power technology capable of exploiting large scale integration fabrication techniques.
CMOS fabrication does however provide a number of challenges to the fabricator in compared to using PMOS or NMOS alone. Specifically, typically independent or separate masking steps are utilized for masking one of the p-type regions while the n-type region is being ion implanted. Also, the n-type regions are separately masked when the p-type regions are being ion implanted or diffusion doped. Accordingly, typical transistor flows use one mask each to form the n-channel and p-channel transistor source and drain regions.
It would be desirable to develop methods which facilitate formation of complementary source and drain regions within a semiconductor substrate, and preferably minimize masking steps in the process.